Adaptive Fail-Safe Power-On Control Circuit

ABSTRACT

A circuit includes an input for receiving power from an external power supply, a voltage regulator coupled to the power input and providing regulated voltage to an external circuit and to the power supply control circuit itself, and a first switch coupled between ground and an Enable input of the voltage regulator. A control input of the first switch is coupled to the regulated voltage, such that when the voltage regulator provides regulated voltage, the first switch is closed, coupling the Enable input to ground, keeping the voltage regulator active. A first switching circuit provides manual activation and deactivation of the voltage regulator; a second switching circuit provides automatic activation of the voltage regulator whenever the power input becomes powered. An intervening circuit prevents the second switching circuit from activating the voltage regulator when the first switching circuit has deactivated it, despite the continued presence of the external power supply.

PRIORITY CLAIM

This application is a divisional application of application Ser. No.15/211,389, filed Jul. 15, 2016, which claims priority to provisionalapplication 62/193,745, filed Jul. 17, 2015, the entire contents ofwhich are hereby incorporated by reference.

BACKGROUND

This disclosure relates to an adaptive fail-safe power-on controlcircuit, and specifically, a power control circuit for an aviationheadset.

SUMMARY

A power supply control circuit includes a power input for receivingpower from an external power supply, a voltage regulator coupled to thepower input and providing regulated voltage to an external circuit andto the power supply control circuit itself, and a first, normally-open,electrically-operated, switch coupled between ground and an active-lowEnable input of the voltage regulator. A control input of the firstswitch is coupled to the regulated voltage, such that when the voltageregulator provides the regulated voltage, the first switch is closed,coupling the Enable input of the voltage regulator to ground, keepingthe voltage regulator active. A first power switching circuit providesmanual activation and deactivation of the voltage regulator; a secondpower switching circuit provides automatic activation of the voltageregulator whenever the power input becomes powered. An interveningcircuit prevents the second power switching circuit from activating thevoltage regulator when the first power switching circuit has deactivatedthe voltage regulator, despite the continued presence of power from theexternal power supply on the power input.

Implementations may include one or more of the following, in anycombination. The intervening circuit may include a second,normally-open, electrically-operated, switch, the second switch beingclosed by the second power switching circuit when the second powerswitching circuit is first activated, and being opened by the secondpower switching circuit when regulated voltage is provided to the secondpower switching circuit. The second switch is connected between anEnable input of the voltage regulator and ground, with a control inputcoupled to an output of the second power switching circuit.

The first power switching circuit may include a third, normally-open,momentary switch coupled between a fourth, normally-closed,electrically-controlled, switch at a first node and an Enable input ofthe voltage regulator at a second node, the fourth switch coupling thefirst node of the third switch to ground such that when both the thirdswitch and the fourth switch are closed, the Enable input of the voltageregulator is coupled to ground, activating the voltage regulator, and acontrol circuit having an input coupled to the first node of the thirdswitch, an output coupled to the control input of the first switch, anda connection to ground, wherein when the voltage regulator provides theregulated voltage, the fourth switch is opened, disconnecting the firstnode of the second switch from ground, and the control circuit isconfigured to deactivate the voltage regulator by coupling the gate ofthe first switch to ground, thus opening the first switch anddisconnecting the Enable input of the voltage regulator from ground. Thecontrol circuit may disable the voltage regulator when the third switchis closed and regulated voltage is present. When regulated voltage ispresent, closing the third switch couples the input of the controlcircuit to the Enable input of the voltage regulator, the Enable inputbeing held at ground by the first switch until the control circuit opensthe first switch. The fourth switch may include a depletion-modejunction field-effect transistor (JFET) that opens upon receivingnegative voltage to its gate from a bias supply powered by the regulatedvoltage.

The second power switching circuit may include a latching circuitcoupled to the power input, the regulated voltage, ground, and a controloutput to the intervening circuit, wherein when power is first receivedon the power input, the latching circuit is latched into a first stateproviding a voltage from the power input to the control output, and whenthe regulated voltage is subsequently received, the latching circuit islatched into a second state connecting the control output to ground. Thelatching circuit may include a first transistor, having a gate connectedto the power input via a first resistor and to the control output, adrain connected to the power input via a second resistor, and a sourceconnected to ground, and a second transistor, having a gate connected tothe drain of the first transistor via a third transistor and to theregulated voltage, a drain connected to the control output, and a sourceconnected to ground, wherein the power supply voltage, in the absence ofthe regulated voltage, activates the first transistor and the controloutput, the first transistor connecting the gate of the secondtransistor to ground through the third resistor, setting the latchingcircuit to the first state, and the regulated voltage, when present,activates the second transistor, which couples the gate of the firsttransistor and the control output to ground, setting the latchingcircuit to the second state. The first and second transistors mayinclude metal-oxide-semiconductor field-effect transistors (MOSFETs). Asecond switch May be interposed between the power input and the latchingcircuit, the second power switching circuit only being active when thesecond switch is closed. The second switch may include ametal-oxide-semiconductor field-effect transistor (MOSFET). The firstswitch may include a metal-oxide-semiconductor field-effect transistor(MOSFET). A battery may be connected to the voltage regulator, whereinthe voltage regulator provides the regulated voltage when enabledregardless of the presence of power on the power input.

The first power switching circuit may be configured to deactivate thevoltage regulator automatically when a related circuit is not in use.The second power switching circuit may includes a latching circuitcoupled to the power input, the regulated voltage, ground, and a controloutput to the intervening circuit, such that when power is firstreceived on the power input, the latching circuit is latched into afirst state providing a voltage from the power input to the controloutput, and when the regulated voltage is subsequently received, thelatching circuit is latched into a second state connecting the controloutput to ground.

In general, in one aspect, an audio source selection circuit forselecting between first and second audio inputs for combining with athird audio input includes a first input receiving an indication thatthe first audio input is active, a second input receiving an indicationthat the second audio input is active, a third input receiving anindication of whether the first or second audio input is prioritized, afourth input receiving an indication of whether the first audio input isin a first mode or a second mode, a first output controlling a firstswitch to couple the first audio input to an audio output, and a secondoutput controlling a second switch to couple the second audio input toan audio output.

Implementations may include one or more of the following, in anycombination. A first NAND gate may have its inputs connected to thefirst and second inputs, producing an output high unless both first andsecond inputs are low; a first, normally open, transistor may have agate coupled to the fourth input, and a source coupled to ground; asecond NAND gate may have both of its inputs connected to a voltagesupply via a resistor, and to the drain of the first transistor througha switch that is open when the third input indicates that the firstaudio input is prioritized and the first transistor; a first NOR gatemay have a first input connected to the output of the first NAND gate,and a second input connected to the voltage supply via the resistor; asecond NOR gate may have a first input connected to the output of thefirst NAND gate, and a second input connected to the output of thesecond NAND gate; a second, normally-open, transistor may have a gatecoupled to the output of the first NOR gate, a source connected toground, and a drain connected to the first output; and a third, normallyopen, transistor may have a gate coupled to the output of the second NORgate, a source connected to ground, and a drain connected to the secondoutput. When the first input is connected to the first output via afirst resistor, and the second input is connected to the second outputvia a second resistor, the first input directly controls the firstoutput, and the second input directly controls the second output, unlessthe corresponding NOR gates close the corresponding transistors.

A prioritization circuit may include a prioritization activation circuitthat determines whether the third audio input is above or below athreshold, and a priority switch having three input states; when thepriority switch is in the first state, the prioritization circuitprovides an enable output regardless of the state of the third input;when the priority switch is in the second state; the prioritizationcircuit provides an enable output only when the third input is below thethreshold; and when the priority switch may be in the third state, theprioritization circuit may not provide the enable output. The first andsecond outputs may include respective first and second AND gates, eachof the first and second AND gates receiving corresponding first orsecond input enable signals at its first input, and receiving the enableoutput from the prioritization circuit at its second input, such thatthe first and second AND gates only activate the respective first orsecond switches if the prioritization circuit provides the enableoutput.

All examples and features mentioned above can be combined in anytechnically possible way. Other features and advantages will be apparentfrom the description and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 4 are circuit diagrams.

DESCRIPTION Automatic and Manual Power Control

A common problem in active noise reduction (ANR) headsets for use inaircraft is that the headsets must be turned on and off—the pilot orpassengers need to be able to turn them off if something goes wrong withthe ANR system, for example. If a headset is configured to simplypower-up when it receives power from the aircraft, the manual power-offcontrol may prevent the headset from powering on the next time theaircraft is started. Some headsets have an automatic power-off feature,when operating from internal battery power, to preserve that battery,which they detect that the headset is not in use, as described in U.S.Pat. Nos. 8,222,641, 8,666,083, and 8,213,625, the entire contents ofwhich are incorporated here by reference. As with the manual on-offcontrol, the auto-off feature may conflict with the auto-on feature. Onegoal of this disclosure is to provide a headset that will power on withthe aircraft radio (or when connected to an already-powered aircraftradio), provide manual on-off control, and to not have the manual andautomatic controls conflict with each other.

A circuit that provides this functionality is shown in FIG. 1. The powermanagement circuit 100 includes a voltage regulator 102 that providespower to the headset 104, as well as to the rest of the power managementcircuit itself. The headset is represented by box 104, which is meantsimply to show that the headset presents a load to the voltageregulator, and has a common ground with the power management circuit.The voltage regulator 102 receives power from an external power supply106, generally the aircraft intercom system (ICS). The voltage regulatormay optionally receive power from a battery 108, to provide power whendisconnected from the ICS or in aircraft where the ICS does not provideoperating voltage to the headset.

The power management circuit 100 has two control circuits 110 and 130,joined by an intervening circuit 150, which in the example of FIG. 1happens to be a single transistor. Control circuit 110 provides manualon-off control, and optionally automatic-off control. It includes amomentary push-button switch 112, a microcontroller 114, a transistor116, a resistors 120, and a bias source 124. The manual control circuit110 is connected to an Enable input 152 of the voltage regulator 102,and receives regulated voltage Vcc from the voltage regulator output154. The manual control circuit is also connected to the gate of atransistor 158, described below.

The transistor 116 is a normally-closed transistor, such as adepletion-mode JFET (junction field effect transistor). The switch 112has two terminals 112 a and 112 b. The first terminal is connected tothe Enable input 152 of the voltage regulator, and the other isconnected to the drain of the transistor 116. When the switch 112 ispressed, this couples the Enable input 152 to ground through thetransistor 116, pulling the Enable input 152 down and activating thevoltage regulator 102. Once activated, the voltage regulator beginsproviding the Vcc voltage, which flows through a pull-up resistor 156 tothe gate of a latch transistor 158. This transistor is a normally-opentransistor, such as an enhancement mode MOSFET. Positive voltage at itsgate activates the transistor 158, closing it and coupling the Enableinput 152 to ground at a second point. This latches the voltageregulator on, as its own output voltage is holding closed the transistorcontrolling its Enable input.

Once the voltage regulator begins supplying Vcc, the bias source 124begins generating a bias voltage that activates the normally-closedtransistor 116, opening it and disconnecting the second terminal of theswitch 112 from the ground. As the Enable input is still held low bytransistor 118, this has the effect of converting the switch 112 into aninput device for the microcontroller 114. When the microcontrollerdetermines that the headset should be turned off, either due to an inputfrom the user on the switch 112, such as holding it in, or due tosoftware or other inputs (not shown) implementing an auto-off function,it couples its control output 114 a to ground. This pulls the gate oftransistor 158 to ground, deactivating that transistor, decoupling theEnable input 152 of the voltage regulator from ground and turning thevoltage regulator off. Once the voltage regulator is turned off, the Vccvoltage is no longer available to hold the transistor 158 closed (evenafter the microcontroller 114 is deactivated), so it will stay off untilre-enabled. The bias source 124 will also be deactivated, allowing thetransistor 116 to close and resetting the control circuit for switch 112to turn the voltage regulator back on when pressed.

The auto-on control circuit 130 includes an optional activation switch132, a pair of transistors 134, 136, and three resistors 138, 140, 142.The control circuit is connected to the external power supply 106, theregulated Vcc voltage 154 (via resistor 160), and the input of theintervening circuit 150. In an initial state, when no voltage ispresent, both transistors 134, 136 are inactive, and therefore open(providing high impedance between their source and drain). When power isfirst received from the external supply 106 (assuming the activationswitch 132 is closed), current flows from the input, through resistors138 and 140, to the inactive Vcc input. Because of the resistor 160between the voltage regulator and the control circuit, these resistorsoperate as a voltage divider, placing a voltage on the gate of thesecond transistor 136 that happens to be about half of the voltagesupplied by the external supply. At the same time, because the gate ofthe first transistor presents a high impedance, the full voltage of theexternal input will also appear there, though the third resistor 142.Because the larger voltage develops on the gate of the first transistor134, it will reach threshold and activate before the second transistor136. As soon as the first transistor 134 is activated, it couples thegate of the second transistor 136 to ground through the resistor 140,stopping it from activating before its gate voltage reaches threshold.

Because the first transistor is activated and the second is deactivated,the output of the control circuit has no path to ground and will followthe external voltage through the third resistor 142. This activates theintervening circuit (described below) to pull the Enable input 152 ofthe voltage regulator low, activating the voltage regulator to supplyVcc on the regulated voltage output 154. Turning on the voltageregulator also provides power to the latching transistor 158, as well asthe microcontroller 114, bias supply 124, and transistor 116 inside themanual control circuit 110. This latches the voltage regulator on andconfigures the switch 112 as an input to the microcontroller just as ifthe system had been turned on manually.

The two transistors of the auto-on control circuit implement anun-clocked flip-flop or latching circuit. After the appearance of Vccfrom the voltage regulator, the voltage at the gate of the secondtransistor 136 will be pulled up to about the mid-point between theregulated and external voltages, well above its threshold. At thispoint, the second transistor will be activated, connecting the gate ofthe first transistor 134 to ground and deactivating it. This reversalconnects the output of the control circuit to ground, deactivating theintervening circuit. Because the voltage regulator is now held enabledby the manual control circuit, disabling the intervening circuit has theeffect of disconnecting the auto-on control circuit from the systemafter it has turned the system on. This allows the user or themicrocontroller to turn the system off without the auto-on systemturning it back on until after external power has also been removed (orthe auto-on activation switch 132 is cycled). That is because, even ifVcc is removed because the headset has been turned off, the dividedexternal voltage at the gate of the second transistor 136 remains abovethreshold, so that transistor stays activated, connecting the gate ofthe first transistor directly to ground, and not allowing the externalvoltage to flip the transistors back to the state where they activatedthe intervening circuit. Once the external voltage is also removed, bothtransistors lose their gate voltage and reset to the initial condition.

As noted, in this example, the intervening circuit 150 is merely asingle, normally-open transistor, such as a MOSFET, with its sourceconnected to ground and its drain connected to the Enable input of thevoltage regulator. When the auto-on control circuit 130 provides avoltage at its output, this activates the transistor, coupling theEnable input 152 of the voltage regulator to ground. When the regulatedVcc voltage flips the state of the the auto-on control circuit, thevoltage at the gate of the intervening circuit transistor goes toground, decoupling the Enable input from ground, but by that time, theEnable input is being held at ground by the manual control circuit 110.

Source Management

In some examples, a headset has inputs for three separate audio sources,the intercom (ICS), Bluetooth (BT) audio, and wired auxiliary audio(AUX). In addition, the BT audio may provide either phone call audio(HFP, for hands-free profile) or stereo audio (A2DP). If more than oneaudio source is available at one time, the system can either mix themtogether, or prioritize one over the other. Some systems choose to lowerthe volume of the lower-priority audio, while others choose todisconnect it entirely. The system described below provides severaldegrees of prioritization. First, ICS audio is prioritized over allother sources, and never disconnected. A user input determines whetheradditional audio sources should be mixed with the ICS, silenced when theICS is active, or shut off entirely. A second user input determinesbetween A2DP and AUX which is to take priority if both of those areactive at the same time. The system assumes that HFP is to take priorityover AUX regardless of this setting, but this could also be changed.

FIG. 2 shows the first stage of this prioritization scheme. Aircraft ICSaudio is received at an aircraft connector 202, where a stereo/monoswitch 204 may allow duplication of a mono signal to both ear cups. TheICS audio passes through un-interrupted to the headphone connector 206.Bluetooth audio system 208 provides two BT audio signals, and providesstatus output signals. An AUX connector 210 provides two AUX audiosignals. The BT and AUX audio are connected to the headphone connector206 by a pair of dual-pole, single-throw switches 212, 214, which are inturn controlled by a pair of AND gates 216, 218. The AND gates arecontrolled by a combination of an ICS priority sub-circuit 220, and asecondary priority sub-circuit 240.

In the ICS priority sub-circuit 220, a priority switch 222 has threepositions, from the top down they are silence, mix, and all-off. In theall-off position, the switch 222 connects an Enable input 224 of the BTsystem to ground, disabling the BT system. In some examples, a separateBT power supply may be present, and the switch may connect an enable ofthat power supply to ground to disable the BT system. The switch 222 inthe all-off position also connects a normally-closed switch 226 betweenVcc and the output of a priority module 228 to ground, opening thatswitch. In the middle, “mix” position, the switch 222 connects a Disableinput of the priority module 228 to ground, stopping the priority modulefrom disconnecting either the BT or the AUX inputs. The switch 226 isleft closed, connecting the Vcc power, through a pull-up resistor 230,to the output 232 of the sub-system, which is connected to the pair ofAND gates 216, 218. With the switch not connecting the BT power supplyEnable input 224 to ground, it is pulled up by Vcc and a pull-upresistor and enabled. Finally, in the bottom, “silence” position, thepriority switch is not connected to anything—the BT power supply andpriority module are enabled, and the output 232 is pulled up by Vcc andthe resistor 230. In this mode, if the priority module determines thatthe ICS is active and secondary audio should be silenced, it pulls theoutput 232 low, deactivating both AND gates 222, 224, and opening bothswitches 226, 228.

Assuming the ICS priority sub-circuit has not disabled the AND gates216, 218, the secondary priority sub-circuit 240 enables one anddisables the other to control which of BT or AUX audio is passed to theheadset. An Aux/BT priority switch 242 determines which of the two takespriority, and an Aux detect circuit 244 determines whether the AUX inputis active. The BT system outputs 246 inform the sub-circuit 240 directlywhether the BT is active and which mode it is in. The operation of thesecondary priority sub-circuit 240 is shown in more detail in FIG. 3.

The circuit in FIG. 3 has inputs AUX Act from the Aux detect circuit244, and BT Act and HFP/A2DP from the BT system. The circuit's outputsare BT ON and AUX ON, which connect to corresponding AND gates 216, 218in the circuit of FIG. 2. The Aux/BT priority switch 242 is shown againfor clarity. In this circuit, the two output lines are connected to thedrains of corresponding transistors 302, 304, which have their sourcesconnected to ground. The outputs are also connected to the correspondingAct inputs, via pull-up resistors 306, 308. The logic gates 310, 312,314, and 316 are configured to activate one or the other of thetransistors to disable the corresponding ON output line. If one of thetransistors is not active, and the corresponding Act input is high, itwill pull the corresponding ON output high.

The first gate 310 is a NAND gate with its inputs coupled to the two Actinputs, and its output coupled to the inputs of the second and thirdgates, 312, 314, both NOR gates. The second gate 312 has its secondinput coupled to the output of the fourth gate 316, another NAND gate,while the third gate has its second input coupled to a voltage high VLDothrough a pull-up resistor 318. The fourth gate 316 has both of itsinputs also connected to the pull-up resistor 318. The three inputsconnected to the pull-up resistor 318 are also connected to the Aux/BTswitch 242, and through it to a transistor 320. The transistor 320 is anormally-open device, such as a MOSFET, and it connects the Aux/BTswitch to ground when it is closed. The gate of the transistor iscontrolled by the HFP/A2DP input 246 via another resistor 322.

Table 1 shows the logic implemented by the circuit of FIG. 3. The inputsare Aux Act, indicating that there is signal on the AUX input, BT Act,indicating the same for Bluetooth, Aux/BT, where the switch is closedwhen AUX is to take priority over Blueooth, as indicated by a logical‘1’, and HFP/A2DP, where a ‘0’ indicates that the current mode is HFPand a ‘1’ indicates that the current mode is A2DP. For the first fivestates in the table, the outputs AUX ON and BT ON mimic the first twoinput columns. If neither input is active, both outputs are disabled.Even though, in this case, NAND gate 310 is outputting a logic ‘1’ toboth NOR gates 312 and 314, which in turn output logic ‘0’ to open thetransistors 302 and 304, since the activity inputs are both also logic‘0’, both outputs remain at ‘0’. If only one input is active, only thatoutput is enabled. Again, the NAND 310 will output a logical ‘1’, soboth NOR gates 312 and 214 output logical ‘0’ and open both transistors302 and 304, but only one of Aux Act or BT Act is ‘1’, so only thecorresponding output will be ‘1’.

The third and fourth columns matter when both inputs are active. In thiscase, the NAND 310 will output a ‘0’, leaving the output of the NORgates in the control of their other inputs. As long as the HFP/A2DPinput shows that the BT connection is A2DP, meaning entertainment audio,the Aux/BT switch controls, enabling AUX if closed and BT if open. Thatis, when the Aux/BT switch is open, the input of NOR gate 314 and bothinputs of NAND gate 316 are pulled up by VLDo and the resistor 318. Thismakes NOR 314 output ‘0’ to enable BT ON (since BT Aux is at ‘1’), whilethe ‘0’ output by NAND 316 combined with the ‘0’ output from NAND 310makes NOR 312 output ‘1’, closing transistor 302 and grounding the AUXON output. When the Aux/BT switch is closed, it connects the input ofNOR gate 314 and both inputs of NAND gate 318 to ground through MOSFET320, so NOR gate 314 outputs a ‘1’ grounding the BT ON output throughMOSFET 304, and NAND gate 316 outputs a 1, causing NOR 312 to output ‘0’and allow the Aux act ‘1’ to bring AUX ON to ‘1’.

If the HFP/A2DP input shows HFP, however, this opens the MOSFET 320,overriding the Aux/BT switch, enabling the BT connection and disablingthe Aux input in the same way as if the Aux/BT switch were open. Inother examples, a single switching device could be used, with its statecontrolled by both the HFP/A2DP line and the state of the Aux/BTpreference, with either HFP mode or BT preference opening the switch.All of the logic implemented by this circuit could alternatively beimplemented using inverted logic and corresponding gate and transistortypes, and it could also be implanted in a programmed device, such as aFPGA, microcontroller, microprocessor, or the like.

TABLE 1 Inputs Outputs AUX BT Aux/BT HFP/A2DP AUX BT act act Closed = 1HFP = 0 ON ON 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 10 1 0 0 1 1 0 1 1 1 1 1 0 1 1 0 1 0 1 1 1 1 0 0 1

FIG. 4 shows one example of the Aux detect circuit 244 from FIG. 2. Inthis example, a high-sensitivity comparator circuit 402 detects thepresence of peaks above a certain threshold (determined by the discretecircuit elements) on the AUX signal line, and provides a pulse stream aslong as the signal includes content above the threshold. This pulsestream is provided to a retriggerable monostable vibrator 404, with atime constant set such that pulses that represent ongoing audio contentwill keep the output AUX Act high, for example, 2.7 seconds. When theaudio stays below the threshold long enough that no peak re-triggers theoutput, the AUX Act output will drop low. This is simply one example ofa circuit that can provide the logical AUX Act signal to the circuit ofFIG. 3, any other suitable audio signal detection scheme would work,such as a programmed digital signal processor, in which both thethreshold signal level and the retriggering time constant could be setin software.

A number of implementations have been described. Nevertheless, it willbe understood that additional modifications may be made withoutdeparting from the scope of the inventive concepts described herein,and, accordingly, other embodiments are within the scope of thefollowing claims.

1-16. (canceled)
 17. An audio source selection circuit for selectingbetween first and second audio inputs for combining with a third audioinput, the selection circuit comprising: a first input receiving anindication that the first audio input is active; a second inputreceiving an indication that the second audio input is active; a thirdinput receiving an indication of whether the first or second audio inputis prioritized; a fourth input receiving an indication of whether thefirst audio input is in a first mode or a second mode; a first outputcontrolling a first switch to couple the first audio input to an audiooutput; and a second output controlling a second switch to couple thesecond audio input to an audio output.
 18. The selection circuit ofclaim 17, further comprising: a first NAND gate with its inputsconnected to the first and second inputs, producing an output highunless both first and second inputs are low; a first, normally open,transistor having a gate coupled to the fourth input, and a sourcecoupled to ground; a second NAND gate with both of its inputs connectedto a voltage supply via a resistor, and to the drain of the firsttransistor through a switch that is open when the third input indicatesthat the first audio input is prioritized and the first transistor; afirst NOR gate with a first input connected to the output of the firstNAND gate, and a second input connected to the voltage supply via theresistor; a second NOR gate with a first input connected to the outputof the first NAND gate, and a second input connected to the output ofthe second NAND gate; a second, normally-open, transistor having a gatecoupled to the output of the first NOR gate, a source connected toground, and a drain connected to the first output; and a third, normallyopen, transistor having a gate coupled to the output of the second NORgate, a source connected to ground, and a drain connected to the secondoutput; wherein the first input is connected to the first output via afirst resistor, and the second input is connected to the second outputvia a second resistor, such that the first input directly controls thefirst output, and the second input directly controls the second output,unless the corresponding NOR gates close the corresponding transistors.19. The selection circuit of claim 17, further comprising aprioritization circuit comprising: a prioritization activation circuitthat determines whether the third audio input is above or below athreshold; and a priority switch having three input states; wherein whenthe priority switch is in the first state, the prioritization circuitprovides an enable output regardless of the state of the third input,when the priority switch is in the second state, the prioritizationcircuit provides an enable output only when the third input is below thethreshold, and when the priority switch is in the third state, theprioritization circuit does not provide the enable output.
 20. Theselection circuit of claim 19, wherein the first and second outputscomprise respective first and second AND gates, each of the first andsecond AND gates receiving corresponding a first or second input enablesignals at its first input, and receiving the enable output from theprioritization circuit at its second input, such that the first andsecond AND gates only activate the respective first or second switchesif the prioritization circuit provides the enable output.